AI's next bottleneck: Why even the best chips made in the U.S. take a round trip to Taiwan

The chip manufacturing sector is facing a critical juncture as advanced packaging emerges as a potential bottleneck for artificial intelligence development. This crucial step involves integrating microchips into hardware that can effectively communicate with external systems, and currently, most of this packaging is concentrated in Asia, leading to capacity shortages. As Taiwan Semiconductor Manufacturing Company (TSMC) prepares to establish two new plants in Arizona, the urgency for expanded advanced packaging capabilities is more pronounced than ever. John VerWey from Georgetown University highlights that without proactive capital investments to support the anticipated surge in fabrication output, the situation could quickly worsen. In a recent interview, Paul Rousseau, head of TSMC North America's packaging solutions, revealed that the demand for advanced packaging techniques, particularly the Chip on Wafer on Substrate (CoWoS) method, is experiencing an impressive 80% compound annual growth rate. Nvidia, a leader in AI technologies, has secured a substantial portion of TSMC's advanced capacity, while Intel, despite facing challenges in attracting significant external clients, has established partnerships with companies like Amazon and Cisco for packaging. Elon Musk has also engaged Intel for custom chip packaging for his ventures, including SpaceX and Tesla, at his planned Terafab facility in Texas. Most of Intel's advanced packaging operations are currently based in Vietnam, Malaysia, and China, though some are conducted in the U.S., specifically in New Mexico and Oregon. As AI demands increase the need for dense, high-performance chips, innovative packaging methods are gaining prominence. Historically, chip packaging was a secondary consideration, but as Patrick Moorhead from Moor Insights & Strategy notes, it has now become as crucial as the chips themselves. TSMC's CoWoS technology is in high demand, leading the company to outsource certain packaging steps to specialized firms. ASE, the largest outsourced semiconductor assembly and test company, anticipates its advanced packaging sales will double by 2026, indicating a robust market growth. TSMC is not only expanding its capabilities in Taiwan but is also working on new facilities in Arizona to reduce turnaround times by eliminating the need for international shipping. The integration of packaging and fabrication processes will be beneficial for manufacturers and customers alike. While TSMC currently packages all its chips in Taiwan, the establishment of local facilities is expected to enhance operational efficiency. Intel is also making strides with its own packaging technology, which includes the embedded multi-die interconnect bridge (EMIB), aiming for cost-effectiveness through strategic silicon placement. Looking ahead, the shift toward 3D packaging techniques presents exciting opportunities for performance enhancements in chip design. With memory and logic chip manufacturers exploring advanced packaging solutions to maximize efficiency, the industry is poised for significant innovation in the coming years.