IBM claims world’s first sub-1 nanometer chip technology

IBM has introduced a groundbreaking chip architecture capable of housing nearly 100 billion transistors within a chip no larger than a human fingernail. This represents a staggering increase in transistor density, nearly doubling that of the company's prior chip technology. This advancement, heralded as the "world's first sub-1 nanometer chip technology," aims to enhance computational power and energy efficiency, especially for AI data centers. Jay Gambetta, director of IBM Research and an IBM Fellow, emphasized the significance of this development during a recent media briefing. He noted that this innovation marks not just an incremental advancement, but a substantial leap toward a future where computing power escalates dramatically without a proportional rise in energy consumption. It's essential to clarify what IBM means by the "world's first sub-1 nanometer chip technology." Due to various physical challenges, creating reliably functioning chips with transistors smaller than 1 nanometer has been deemed impractical. Thus, IBM posits that its new "nanostack" architecture can achieve performance enhancements similar to what would be expected from a hypothetical chip featuring dimensions below 1 nanometer. Specifically, the company's latest chip technology operates at the 0.7-nanometer node, referred to as the 7 angstrom node, since one nanometer equals 10 angstroms. However, it’s crucial to note that these node numbers do not correspond to the actual physical sizes of IBM’s chip features. Unlike older chip generations from the 1970s and 1980s, which had dimensions that matched their node designations, this has not been the case for many years, especially with the latest chips produced using 3-nanometer or 2-nanometer processes.